Taking memory hard IP core as an example, this paper studies the test technology based on test evaluation circuit. Considering the timing constraints of the chip, the design methods for the universality and reusability of the hard IP core are studied. At the same time, based on the hard IP core test and verification environment, the control constraints and boundary conditions of hard IP core are obtained, and the test and verification of hard IP core function and performance are actually evaluated.
4.1. Memory Hard IP Core Function and Performance Testing and Verification
As embedded SOC design based on reusable memory hard IP core gradually becomes the mainstream of IC design, the area of memory hard IP core in SOC is increasing. Usually, the test method of memory hard IP core analyzes its physical fault defects according to its structural, transform the physical fault defects into logical faults, and use fixed logical fault model to analyze these defects. At present, the functional fault models mainly include following categories : stuck at fault (SAF), stuck open fault (SOF), transition fault (TF), coupling fault (CF) and address fault (AF). Stuck faults can be divided into faults with memory cells stuck at 1 or 0.
According to different fault models, some specific states are selected, and the test information of these states are compiled into a test algorithm. The selection of memory chip test algorithm is determined by the coverage of the fault model [12-13]. That is, an effective test algorithm covering the fault model which proves whether the memory unit can erase, read and write normally is need to choose to test this memory chip. At present, the commonly used test algorithms include : all "0" and all "1", Checkerboard, Gallop, March, Walk, Masest, Movi, etc.
In addition to the functional testing of memory hard IP core, it is also necessary to test its timing performance. The performance characteristic parameters of memory hard IP core generally need to be tested include read and write timing, such as clock cycle (tcyc), address setup time (tas), address hold time (tah), etc. As shown in Figure 3, is a SRAM timing diagram, in which CLK is a clock signal, A is an address signal, and Q is a data output signal, CEN is chip enable signal, WEN is the write enable signal.
Memory timing diagram.
4.2. Hard IP Core Test and Verification Based on On-Chip Evaluation Circuit
In this paper, two SRAM hard IP core testing based on the general evaluation system is completed to meet the requirement of hard IP core performance test. The input data setup time, address and control signal setup time, input data hold time, address and control signal hold time of SRAM hard IP core are tested by ATE and the customized evaluation system. The ring oscillator module, frequency dividing module and self-calibration module are also tested.
Two SRAM hard IP core chips are designed at the same time. Chip A is a normal SRAM hard IP core chip. The input and output of SRAM hard IP core are connected with corresponding driving circuits. Chip B contains a general evaluation circuit, which is mainly including three parts: the programmable master behavior simulation unit, the configurable on-chip interface module and the configurable output timing detection module. At the same time, it integrates the target tested SRAM hard IP core, the test I/O group and other clock circuits to form a standardized on-chip hard IP core evaluation circuit system. The programmable master control behavior simulation unit is the key part of the system. By applying reasonable external control incentives and internal simulation control procedures, it can perform read-write and other actions to the SRAM hare IP core, and collect corresponding feedback signals based on the on-chip read-write protocol to verify its functional correctness. Moreover, it generates timing signal by using the control unit, combined with the configurable input and output module loaded on the periphery of the SRAM hard IP core, and then uses the configurable output timing detection module, which is composed of D flip-flop chains, to collect the timing signal through the SRAM hard IP core output port. The SRAM hard IP core test results are obtained by measuring and extracting the timing signal through the ATE, so as to realize the testing and performance evaluation of the SRAM hard IP core.
The SRAM hard IP core capacity of the two chips both are 64K (4k x 16bit), the operating voltage is 1.2V, and the maximum operating frequency is 150MHz. The functional block diagrams of the two chips are shown in Figure 4 and Figure 5. The size of these two chips both are 4 997.184μm *3 998.364μm (excluding scribe line). The bonding pad size is 66μm *66μm.
The functional block diagram of chip A. Figure 5.
The functional block diagram of chip B.
According to the specific characteristics of the chip and the requirement of timing accuracy, the timing performance of SRAM hard IP core will be tested mainly by using timing edge scanning test, Digitizers sampling analysis, Time-Domain Reflectometry (TDR) timing calibration and compensation and other methods of ATE. The two chips are tested and verified by V93000 tester (made by Advantest Company of Japan). Each PS1600 digital board of the tester has 128 test channels, the depth of test vectors is 112 M lines, the timing resolution is 1 pS, and the timing accuracy is 80 pS. It can effectively support the test of hard IP core timing parameters . The prober card of these two chips is shown in Figure 6.
Tested chip prober card.
Chip A and chip B are tested separately. Taking address setup time as an example, chip A adopts the general test method of AC parameters, and the test result is about 1nS. Chip B is tested by ATE combined with evaluation circuit. There are two delay chains DL1 and DL2 in the evaluation circuit, and the delay time can be adjusted by DL1_BSEL_PAD, DL1_LSEL_PAD, DL2_BSEL_PAD and DL2_ LSEL_ PAD these four signals, among which DL1_BSEL_PAD and DL2_LSEL_ PAD signal are used for coarse tuning and DL1_LSEL_PAD and DL2_ LSEL_ PAD signals are used for fine tuning. In the initial state, the delay time of two delay chains is set to be the same, then keep the delay of DL2 unchanged while testing, and increase the delay of DL1 continuously, if the output of SRAM_Q4FSM is 0, the delay between the two delay chains does not satisfy the setup time. When the output becomes 1, the delay satisfies the setup time.
According to the test specifications, power on the chip, set the required pins in high and low states, and float all the rest unused pins, apply address and clock signals to AX_IN_PAD and CLK_IN_PAD. If SRAM_Q4FSM is high level for a period of time, record the values of DL1_BSEL_PAD and DL1_LSEL_PAD respectively, which represents the time of two square wave signals’ timing edge when they can be identified by the edge-triggered D Flip-flop chain in the chip, and then the address setup time of the chip can be calculated. The chip is tested on V93000 test platform. The address setup time test diagram is shown in Figure 7. Through the above test methods, the address setup time parameters of 10 chips (5 chip A and 5 chip B) were tested three times, and the data results are shown in Table 1. The test accuracy of chip A is about nS level while the test accuracy of chip B can reach pS level.
The address setup time test diagram. Table 1.
Address setup time test results of the chip.
|Chip||Chip A||Chip B|