It has been almost a decade since the first fin field-effect transistor (FinFET) technology was commercialized. Owing to the superior electrostatic integrity, FinFET technology has demonstrated significant advantages over conventional planar devices to extend Moore’s law, and is now being adopted by all the leading semiconductor manufacturers for low-power and high-performance applications ^[1–3]. However, with continuing aggressive technology scaling, the impact of the undesirable parasitic resistance and capacitance becomes increasingly prominent and even outpaces other device aspects at advanced FinFET nodes ^{[4, 5]}. Selective epitaxial growth of silicon (Si) and silicon germanium (SiGe) layers in the recessed source/drain (S/D) cavity regions is essential to improve FinFET drive current by reducing the parasitic resistance, but it also raises the parasitic capacitance between the metal gate and S/D electrodes, which may adversely impact the performance at the circuit level ^[6–9]. Therefore, the trade-off between the parasitic resistance and capacitance must be considered to optimize FinFET performance. In this study, for the first time, we report the impact of the recessed S/D cavity structure on p-channel FinFET (pFET) performance on a fully integrated advanced FinFET platform, and we demonstrate an extra process knob of applying an ion implantation process after the cavity formation for pFET performance enhancement.

A fully integrated advanced bulk FinFET complementary metal-oxide semiconductor (CMOS) platform was adopted to perform this study. Figure 1(a) depicts the schematic process flow of advanced bulk FinFET fabrication ^[10]. After the formation of fin and dummy gate structures, low-dielectric constant (low-k) films were deposited over the wafer using an atomic layer deposition (ALD) process to form gate sidewall spacers ^{[11, 12]}. A reactive ion etching (RIE) process was then applied to form recessed cavity structures in the S/D regions for the subsequent epitaxy (EPI) processes. The S/D cavity formation process was comprised of three steps: removing the spacer from the top of the fin, recessing the exposed fin by an anisotropic etching process, and setting the final cavity geometry by an isotropic etching process. In the first step, the amount of the spacer pulldown on the fin is a critical parameter to control the lateral width of S/D EPI ^[13]. The second anisotropic etching step is the main step to recess the fin vertically along the gate sidewall spacer, and the third isotropic etching step is the final step to further etch the fin vertically and laterally under the spacer to achieve the desired cavity geometry. Figure 1(b) shows the typical cavity profile of a pFET device, the cavity depth is defined as the distance from the top of the fin to the bottom of the cavity, and the cavity proximity is defined as the distance from the lateral edge of the cavity to the edge of the gate. Following the cavity formation, S/D EPI processes were optimized according to the cavity geometry to achieve the desired EPI geometry, then the replacement metal gate (RMG) and metal contact formation processes were performed to complete FinFET fabrication. In this study, pFET devices with a range of cavity depth and proximity targets were fabricated by modifying the etching time of each individual step of the cavity formation process, in-situ boron (B) doped SiGe EPI was formed in the recessed cavity regions as the stressor to enhance the hole mobility ^[14–17]. The impact of applying a low-energy B ion implantation process in the S/D cavity regions before SiGe EPI formation was also investigated.

The pFET devices under study were based on a dense 2-fin standard logic cell, and the electrical tests were performed at the metal one (M1) level with the supply voltage V_dd = 0.75V. Device on-resistance (R_ON) was measured at the linear region with the overdrive gate voltage of 0.7V, and drain-induced barrier lowering (DIBL) was measured at a fixed current density of 10nA/um. To decouple the threshold voltage (V_T) impact, effective current (I_EFF) at the target off-current density (I_OFF) of 11nA/um was characterized as the device metric for transistor current drivability. Since the gate electrode is wrapped around the channel in FinFET devices, the resistance and current in this study were normalized by the effective gate width of 91nm per fin. In addition, a capacitor array structure at zero gate bias was adopted to characterize the overlap capacitance (C_OV) between the gate and S/D electrodes through the gate oxide and sidewall spacer. C_OV is a clear indicator of the S/D junction placement with respect to the gate electrode, and it is a major component of the overall effective capacitance, therefore C_OV should also be considered in order to optimize the performance at the circuit level.

In this study, the impact of the recessed S/D cavity structure on the performance of pFET devices on a fully integrated advanced FinFET platform is reported for the first time. S/D cavity depth and proximity were modulated around the optimal reference point by tuning the cavity formation etching process, and an extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile. Device characteristics were discussed and guidelines to enhance the device performance by optimizing the S/D cavity structure were provided considering the trade-off between the S/D resistance and short channel effect, as well as the impact of the parasitic capacitance on the circuit-level performance.