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Current Status of the Integrated Circuit Industry in China ― Overview of Semiconductor Materials Industry
Authors: Litho World
Keywords:IC Industry;Material lndustry
doi:10.33079/jomm.20030106
Issue 1: 20030106, 2020 | PDF
Research Article
Published: March 30, 2020
Views:25
Abstract: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momen...
A Device Design for 5 nm Logic FinFET Technology
Authors: Yu Ding, Yongfeng Cao, Xin Luo et al.
Institution:Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai
Keywords:5nm FinFET;brief process flow;key dimensions;simulated device DC/AC performance;RO PPA performance
doi:10.33079/jomm.20030105
Issue 1: 20030105, 2020 | PDF
Research Article
Published: March 30, 2020
Views:28
Abstract: With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, N...
A Study of 2D Assist Feature Placement
Authors: Liang Zhu, Barry Ma, Lin Shen et al.
Institution:Synopsys Inc., 1027 ChangNing Road, Shanghai, China, 200050
Keywords:Assist Feature;Inverse Lithography Technology;Low K1 Lithography;Machine Learning
doi:10.33079/jomm.20030104
Issue 1: 20030104, 2020 | PDF
Research Article
Published: March 30, 2020
Views:19
Abstract: Sub-resolution assist features have been widely recognized in lithography patterning. In general, the insertion of assist features in optically adjacent space around main designed features, will ch...
Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography
Authors: Yushu Yang, Yanli Li, Qiang Wu et al.
Institution:Shanghai IC R&D Center, 497, Gaosi Road, Zhangjiang Hi, -, Tech Park, Shanghai
Keywords:5 nm Logic Process;EUV;metal gate cut;SAC;BAC;self-aligned LELE
doi:10.33079/jomm.20030103
Issue 1: 20030103, 2020 | PDF
Research Article
Published: March 30, 2020
Views:94
Abstract: 5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries. In a typical 5 nm logic process, the Fin pitch is 22~27 nm, the contact-poly pi...
Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing
Authors: Wei Zhang, Jun Xu, Sicong Wang et al.
Institution:Yangtze Memory Technologies Co., Ltd., Wuhan
Keywords:3D NAND;Metrology;Semiconductor;HAR;Process Control
doi:10.33079/jomm.20030102
Issue 1: 20030102, 2020 | PDF
Research Article
Published: March 30, 2020
Views:33
Abstract: 3D NAND technical development and manufacturing face many challenges to scale down their devices, and metrology stands out as much more difficult at each turn. Unlike planar NAND, 3D NAND has a thr...
DFM: “Design for Manufacturing” or “Design Friendly Manufacturing”
Authors: Wenzhan Zhou, Hung-Wen Chao, Yu Zhang et al.
Institution:Shanghai Huali Integrated Circuit Corp, China
Keywords:Design for Manufacturing (DFM);Design Friendly Manufacturing;EUV Lithography;Source Mask Optimization (SMO);Design Technology Co-optimization (DTCO);Process Window;Process Variation
doi:10.33079/jomm.20030101
Issue 1: 20030101, 2020 | PDF
Research Article
Published: March 30, 2020
Views:101
Abstract: As the IC manufacturing enter sub 20nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. However, by introducing newly designed hardware (1980i etc.) pro...
Current Status of the Integrated Circuit Industry in China Packaging and Testing Industry Review
Authors: Litho World
Keywords:Packaging;Testing Industry
doi:10.33079/jomm.19020409
Issue 4: 19020409, 2019 | PDF
Research Article
Published: Dec. 30, 2019
Views:244
Abstract: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momen...
Dual Micro-power 150mA Ultra LDO CMOS Regulator with fast startup
Authors: Peng Zheng, Hai-Shi Wang
Institution:Chengdu University of Information Technology, Chengdu
Keywords:low dropout regulator (LDO);dual micro-power;ultra
doi:10.33079/jomm.19020402
Issue 4: 19020402, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:268
Abstract: This paper presents a dual micro-power 150mA ultra LDO CMOS regulator, which is designed for high performance and small size portable wireless devices. The proposed LDO has been designed and simula...
A Simulation Study for Typical Design Rule Patterns in 5 nm Logic Process with EUV Photolithographic Process
Authors: Yanli Li, Qiang Wu, Shoumian Chen
Institution:Shanghai IC R, &, D Center, 497, Gaosi Road, Zhangjiang Hi, -, Tech Park, China
Keywords:5nm design rule;minimum area;minimum exposure latitude;aberration;shadowing effect
doi:10.33079/jomm.19020406
Issue 3: 19020406, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:194
Abstract: 5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet (EUV) lithography on a large scale. We have done a simulation study for typical 5 nm logic design ...
The Effect of Fin Structure in 5 nm FinFET Technology
Authors: Enming Shang, Yu Ding, Wenqiao Chen et al.
Institution:Shanghai IC R, &, D Center, Shanghai
Keywords:5 nm;FinFET;fin profile;semiconductor
doi:10.33079/jomm.19020405
Issue 4: 19020405, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:264
Abstract: In 5 nm technology node, FinFET device performance is sensitive to the dimension of the device structure such as the fin profile. In this work, we simulate the influence of fin height and fin width...