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Generative Learning in VLSI Design for Manufacturability: Current Status and Future Directions
Authors: Mohamed Baker Alawieh, Yibo Lin, Wei Ye et al.
Institution:Electrical and Computer Engineering, University of Texas at Austin, Austin
Keywords:Design for Manufacturability;Generative Learning;Machine Learning;Lithography
doi:10.33079/jomm.19020401
Volume 2, Issue 4: 19020401, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:214
Abstract: With the continuous scaling of integrated circuit technologies, design for manufacturability (DFM) is becoming more critical, yet more challenging. Alongside, recent advances in machine learning ha...
A Photolithography Process Design for 5 nm Logic Process Flow
Authors: Qiang Wu, Yanli Li, Yushu Yang et al.
Institution:Shanghai IC R, &, D Center, 497, Gaosi Road, Zhangjiang Hi, -, Tech Park, China
Keywords:5 nm Logic Process;EUV;SADP;self-aligned LELE;RCWA;stochastics;mask 3D scattering
doi:10.33079/jomm.19020408
Volume 2, Issue 4: 19020408, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:183
Abstract: With the introduction of EUV lithography, the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method. In a typical 5 nm logic process, the contact-po...
Dual Micro-power 150mA Ultra LDO CMOS Regulator with fast startup
Authors: Peng Zheng, Hai-Shi Wang
Institution:Chengdu University of Information Technology, Chengdu
Keywords:low dropout regulator (LDO);dual micro-power;ultra
doi:10.33079/jomm.19020402
Volume 2, Issue 4: 19020402, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:137
Abstract: This paper presents a dual micro-power 150mA ultra LDO CMOS regulator, which is designed for high performance and small size portable wireless devices. The proposed LDO has been designed and simula...
Novel Pattern-Centric Solution for XtackingTM AFM Metrology
Authors: Sicong Wang, Jian Mi, Abhishek Vikram et al.
Institution:Yangtze Memory Technologies Co, ., Ltd, Wuhan
Keywords:VIA;Dishing;AFM;Image;Metrology;3D NAND
doi:10.33079/jomm.19020403
Volume 2, Issue 4: 19020403, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:117
Abstract: 3D NAND (three-dimensional NAND type) has rapidly become the standard technology for enterprise flash memories, and is also gaining widespread use in other applications. Continued manufacturing pro...
Self-assembly of Blended PS-b-P2VP Block Copolymers
Authors: Baolin Zhang, Yu Chen, Shisheng Xiong
Institution:School of Information Science and Technology, Fudan University, Shanghai
Keywords:Micro-phase;blending;lamellar pattern;solvent annealing;sequential infiltration synthesis
doi:10.33079/jomm.19020404
Volume 2, Issue 4: 19020404, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:154
Abstract: Directed Self-Assembly (DSA) of block copolymers (BCPs) is a promising technique for sub-10 nm nanofabrication, which is highly compatible with conventional lithography. DSA relies on the microphas...
The Effect of Fin Structure in 5 nm FinFET Technology
Authors: Enming Shang, Yu Ding, Wenqiao Chen et al.
Institution:Shanghai IC R, &, D Center, Shanghai
Keywords:5 nm;FinFET;fin profile;semiconductor
doi:10.33079/jomm.19020405
Volume 2, Issue 4: 19020405, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:126
Abstract: In 5 nm technology node, FinFET device performance is sensitive to the dimension of the device structure such as the fin profile. In this work, we simulate the influence of fin height and fin width...
A Simulation Study for Typical Design Rule Patterns in 5 nm Logic Process with EUV Photolithographic Process
Authors: Yanli Li, Qiang Wu, Shoumian Chen
Institution:Shanghai IC R, &, D Center, 497, Gaosi Road, Zhangjiang Hi, -, Tech Park, China
Keywords:5nm design rule;minimum area;minimum exposure latitude;aberration;shadowing effect
doi:10.33079/jomm.19020406
Volume 2, Issue 3: 19020406, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:95
Abstract: 5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet (EUV) lithography on a large scale. We have done a simulation study for typical 5 nm logic design ...
White Light Interference Solution for Novel 3D NAND VIA Dishing Metrology
Authors: Xiaoye Ding, Sicong Wang, Yi Zhou et al.
Institution:Yangtze Memory Technologies Co, ., Ltd, Wuhan
Keywords:WLI;Dishing;Metrology;3D NAND;Bonding
doi:10.33079/jomm.19020407
Volume 2, Issue 4: 19020407, 2019 | PDF
Research Article
Published: Dec. 25, 2019
Views:95
Abstract: In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher...
Current Status of the Integrated Circuit Industry in China Packaging and Testing Industry Review
Authors: Litho World
Keywords:Packaging;Testing Industry
doi:10.33079/jomm.19020409
Volume 2, Issue 4: 19020409, 2019 | PDF
Research Article
Published: Dec. 30, 2019
Views:144
Abstract: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momen...